The present invention, in some embodiments thereof, relates to a multi-topology logic gate and, more particularly, but not exclusively, to operation of multi-topology logic circuits.
The use of cryptographic devices storing sensitive information securely has substantially increased in the last decades, and in the foreseen future this trend is probably about to continue. Devices such as smart cards, mobile devices, radio frequency identification (RFID), and wireless sensor networks (WSN), are implemented in various applications [2-4]. In order to handle a very wide variety of threats, these devices, in most cases, include a multi-level security protection. Usually, the security system comprises an authentication block, and depending on the application, also a cryptographic block. Essentially, the purpose of the cryptographic block is to encrypt the plaintext to be sent, according to some cryptographic algorithm and secret key, and vice versa.
The security sensitive applications face different kinds of threats today. The mathematical/software attacks try to reveal the device key by using the plaintext, the ciphertext, or both [5]. In contrast, side-channel attacks, brought into attention slightly more than a decade ago [1,6,7], exploit and misuse the information related to the physical behavior of these devices, such as: operation time, power consumption, or emitted electromagnetic radiations.
Such attacks may be performed in a form of simple power analysis (SPA), which includes just few measurements but requires much knowledge regarding the ASIC implementation, or more dangerous but time consuming differential power analysis (DPA) which includes a large number of measurements, assuming less regarding the ASIC implementation [8].
The aforementioned attacks have lead researchers and commercial companies to develop many countermeasures against them, of which the common principle is breaking the connection between the instantaneous power consumption and the intermediate processed data in the ASIC crypto-core. This includes algorithmic or system approaches that are based on correlation reduction between the performed operation and circuit activity, such as: an addition of dummy operations, averaging the activities of the different processing steps [9], a randomization of crypto-operation execution [10]. Another algorithmic approach called blinding uses an internal random generation and masking the processed data with the random numbers using mathematical operation like exclusive-or operation [11]. The disadvantages of these methods are higher power consumption and area. Additionally, these methods are still vulnerable to higher-order DPA attacks [12].
Similar to algorithmic methodologies, the hardware redesign methods could be utilized, where the goal is averaging the power consumption per clock cycle. This can be achieved by addition of “dummy” gates, which draw always the same amount of current regardless of its inputs [12]. The disadvantage of these techniques is a big energy consumption overhead that is introduced. Another method is based on use of dynamic differential logic. Dynamic differential logic has the constant current consumption independent from the switching type (0 to 1 or 1 to 0). There are different variants of this approach including Sense Amplifier Based Logic (SABL) [13], and Wave Dynamic Differential Logic (WDDL) [14].
Although many logic families, such as CMOS, PTL, Domino, GDI, DML and others [15-18] have been proposed in the literature, only a few of them were identified as candidates to improve the resistance to power attacks.
Useful and important metrics for analyzing and evaluating the effectiveness of a DPA attack are the inter-signal SNR (SNRINTER), described in [19], and the use of information theoretic tools (e.g., mutual information), described in [12]-[25]. The SNRINTER indicates the difficulty of the recognition of the correct key from the wrong keys. Referring to the information theoretic tools, the amount of information that leaks from the circuit when it processes data is evaluated. The mutual information between the inputs to the circuit and the power consumed is examined. These information theoretic tools help us to divide the security problem into two orthogonal problems: evaluation of the actual information that leaks from the circuit, and supposition of how an attacker can (or cannot) model and use it to find the correct key.